Logical circuits are not capable of high-speed circuit operations unless signal transmission delays are properly controlled. Typical among such problems is a problem of clock skew concerning synchronous circuits. Usually in the synchronous circuit clock signals synchronize operations of a plurality of elements, but in the case where signal supplying paths from a source of a clock signal to respective destinations differ in delays in signal transmission, difference in the delays, that is, the clock skew, causes an operation speed of the circuit to lower, or hinders normal operations of the circuit.
In light of such a problem, the Japanese Publication for Laid-Open Patent Application No. 6-215071/1994 (Tokukaihei No. 6-215071) discloses a clock routing design apparatus which controls wire lengths. As illustrated in FIG. 16, the apparatus determines a route so that wire lengths from a clock driver 101 as a source of the clock signal to respective blocks 102 through 105 as destinations are equal to each other.
On the other hand, the Japanese Publication for Laid-Open Patent Application 6-89938/1994 (Tokukaihei 6-89938) discloses a method for adjusting delays so that differences in delays in signal transmission through the signal supplying paths are absorbed. As illustrated in FIG. 17, an apparatus to which the method is applied includes delay adjusting circuits 117 having driving ability. The adjusting circuits 117 are provided between a clock signal source ill and logical circuits 113 through 116 in a logical circuit section 112, which are destinations of signal supply. According to the method, a plurality of the delay adjusting circuits 117 are prepared, and one delay adjusting circuit 117 with which no difference in the delays occurs is selected among them, based on simulations.
Incidentally, the layout of such circuitry as described above has conventionally been carried out in a procedure illustrated in FIG. 18, for example.
First of all, each cell is placed at each desired position (S101), and then, wires for supplying a signal to which delay adjustment is applied are provided between a signal source and each cell (S102). Subsequently, other wires are provided where necessary (S103), and parasitic components such as wire resistance and wire capacitance are extracted (S104). In addition, signal timings are examined regarding whether or not signal delays are controlled as designed in a state where the routing is completed (S105). Here, in the case where the signal delays are not controlled as designed, the routing is corrected based on the extracted parasitic components (S106), and anew extraction of parasitic components is carried out (S104).
In the routing design by the apparatus disclosed by the former publication wherein the respective wire lengths are set equal, some of the wires are necessarily roundabout wires such as a wire connected to the block 102. Therefore, arises a problem that areas of electronic circuit components expand, or a problem that power consumption increases. Besides, since influences of wire resistances and wire capacitances are great due to further miniaturization of elements in integrated circuits such as LSIs, delays cannot be properly controlled only by setting wire lengths equal, in a delay model wherein the wire resistances and the wire capacitances are to be taken into consideration. Furthermore, in the case where the capacitances of the wires to which signal delay adjustment is applied are caused to change due to influences of the other wires and as a result the delays are caused to change, differences between the delays due to such changes cannot be adjusted.
On the other hand, according to the method disclosed by the latter publication whereby among the prepared delay adjusting circuits 117 an optimal one is selected, influences of the other wires are reflected in the selection. However, the delay adjusting circuits 117 and the logical circuits 113 through 116 are provided in respective areas, thereby causing the wires therebetween to become longer. This causes areas necessary for the routing to expand as well as causes wire capacitances to increase. Since the delay adjusting circuits 117 are required to have higher driving abilities as the wire capacitances increase, the wire capacitances and the delay adjusting circuits 117 both become load capacitances, thereby causing the power consumption to increase.
On top of that, according to the latter method whereby an optimal one is selected among the already-fixed delay adjusting circuits 117, the other delay adjusting circuits 117 which are not selected are wasted. Since a plurality of delay adjusting circuits 117 are provided as multiple choices with respect to each of the logical circuits 113 through 116, the wasted delay adjusting circuits 117 increase as the logical circuits increase. In addition, in the case where a clock signal is supplied through one delay adjusting circuit 117 to a plurality of logical circuits, the delays due to the respective paths cannot be individually adjusted.
Furthermore, the circuitry layout in the procedure described above is time-consuming and less efficient, since the routing is once carried out and thereafter it is repeatedly corrected so that a desirable delay control is achieved.